Job Location: Bangalore
Minimum qualifications:
- Bachelor’s degree in Electrical, Electronic or Computer Engineering, a related field or equivalent practical experience.
- 7 years of experience in the area of ATE test patterns generation, silicon bring up, and diagnosis of mobile chips, processors, and SoC designs.
- Experience with standard protocols such as IEEE 1149.1 JTAG, SPI, MDIO, DDR, APB, AXI, etc.
Preferred qualifications:
- Experience in the area of digital verification and direct experience with industry tools such as Synopsys VCS, Cadence Xcelium for generation of both directed and random tests and using different waveform viewer tools for interactive debug.
- Experience in scripting languages (Python, Tcl) and CAD automation tools.
- Familiar with different test patterns formats such as STIL, WGL, SVF, VCD, eVCD and ATE fail datalogs.
- Strong understanding of System Verilog based verification and generation of both directed and random tests with coverage reporting.
- Familiar with UVM based verification methodology along with creating assertions.
About the job
Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.
As a member of the Design for Testing (DFT) Productization team in Product and Test Engineering group, you will be mainly responsible for the generation, bring up, and debug tasks for the functional test patterns on both automated test equipment (ATE) and on the system level bench platforms. You will work with ASIC Architecture, Design, DFT, Pre-silicon SOC Verification groups to define test methodologies and build complex verification infrastructure. The main goal is to enable development of high test coverage and most test time and test vector memory optimized ATE functional test patterns and ensure these test patterns are production worthy.
Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.
Responsibilities
- Develop verification infrastructure and generate functional test patterns for complex cores for the purpose of test coverage improvements, power, performance, and timing characterization and support all ATE and bench level bring up and debug tasks.
- Develop test cases to exercise HSIOs on ATE and system level bench platforms.
- Perform extensive zero-delay and SDF back-annotated simulations of ATE test patterns and resolve any simulation issues.
- Provide support to develop new test patterns for critical RMA debug and failure analysis.
- Run power aware gate level simulations to validate low power content in the designs.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google’s EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.
https://bigdatakb.com/google-hiring-design-engineer-design-for-testing-productization-bigdatakb-com-28-jan-22/
Submit CV To All Data Science Job Consultants Across India For Free