Cyient is a global engineering and technology solutions company. As a Design, Build, and Maintain partner for leading organizations worldwide, we take solution ownership across the value chain to help clients focus on their core, innovate, and stay ahead of the curve. We leverage digital technologies, advanced analytics capabilities, and our domain knowledge and technical expertise, to solve complex business problems.
With over 15,000 employees globally, we partner with clients to operate as part of their extended team in ways that best suit their organization’s culture and requirements. Our industry focus includes aerospace and defence, healthcare, telecommunications, rail transportation, semiconductor, geospatial, industrial, and energy.
BE/Btech or ME Mtech Fresher
Trained from reputed institutions in Analog, Digital, Mixed Signal verification, SV, UVM, VerilogAMS,
Good knowledge in Analog basic circuits like CMOS inverter, Op Amps, Bandgap, Current mirror, Diff-Amps, etc..
Good knowledge in DIGITAL circuits like basic gates, mux, Flip-Flops etc..
Spice netlist simulations experience is added advantage
Scripting languages like PERL, Python is added advantage.
Skills & Experience
AMS Verification, Digital Verification, Freshers, PSPICE or Equivalent Analog Circuit Simulation Tool Experience, System Verilog, Verilog, Verilog-AMS
Cyient is an Equal Opportunity Employer.
Cyient recruits, employs, trains, compensates, and promotes regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender, gender identity or expression, veteran status, and other protected status as required by applicable law. We are proud to be a diverse and inclusive company where our people can focus their whole self on solving problems that matter.